As semiconductor devices, such as integrated circuits, become more and more complex, additional individual components are included in the device for increased performance and cost effectiveness. It is necessary that individual components in devices be made increasingly small and tightly packed to avoid excessive increases in the size of the devices as the number of individual components increases. For example, integrated circuits which were once made with conductive lines having widths on the order of 2 .mu.m had hundreds of thousands of transistors. Many integrated circuits now have over a million transistors. To prevent the integrated circuit size from growing proportionately with the number of transistors, the width of conductive lines used to make the transistor was reduced to on the order of 0.5 .mu.m. As device performance and complexity increases, these line widths are expected to be made even narrower.
With feature sizes decreasing, it is becoming more difficult for semiconductor manufactures to align one feature relative to another and to control size tolerance as a function of nominal feature size. To overcome this difficulty, manufacturers try to incorporate as many self-aligned features in the manufacturing process as possible. However, some features make self-alignment or alignment insensitivity very complex or expensive to achieve. For instance, semiconductor devices often include two or more metal layers which are separated by one or more dielectric layers. In some portions of the device, it is necessary to make contact between the two metal layers. Most conventional device manufacturing processes do not have self-aligned processes for making contact between a first metal layer and a second metal layer. Because self-aligned first metal-to-second metal contacts are not typically used, and because features sizes of the first and second metal layers are becoming smaller, contact alignment is exceedingly critical and difficult. Any misalignment of the contact may result in short circuiting the second metal layer to a conductive feature other than, or in addition to, the first metal layer.
One method in which semiconductor manufacturers have overcome alignment difficulties is by creating a conductive landing pad in a metal line of the first metal layer. The conductive landing pad is made wider than the minimum metal width to provide additional contacting area, thereby establishing an additional alignment tolerance. A semiconductor device 10 utilizing a conductive landing pad is illustrated in FIG. 1. A cross-sectional view of device 10 taken along the line 2--2 of FIG. 1 is illustrated in FIG. 2. Device 10 includes a first metal line 12 made from a first metal layer and an overlying second metal line 14 made from a second metal layer. As indicated in FIG. 2, the two metal lines overly a substrate 11, which is typically silicon or another semiconducting material. A first dielectric layer 13 electrically isolates first metal line 12 from substrate 11, and a second dielectric layer 15 electrically isolates the first metal line from overlying conductive layers which may be present. In conventional semiconductor devices there may also be several other intervening layers between the first and second metal layers and the substrate, but for the sake of clarity only first and second dielectric layers 13 and 15, respectively, are illustrated. To make contact between the first and second metal lines, a contact opening or via 16 is formed in second dielectric layer 15 using conventional lithography and etching techniques. Upon depositing the second metal layer, the second metal fills via 16, thereby creating an electrical contact between first metal line 12 and second metal line 14.
In order to establish a good and reliable electrical contact between the two layers, it is desirable to make via 16 as large as possible to maximize the contact area between the two metal layers. A maximum contact area minimizes contact resistance and improves signal quality and speed between conductive layers. As illustrated in FIG. 1, the diameter of via 16 is nearly equal to the minimum width of first metal line 12. Because the size of the via is very close to that of a minimum line, there is very little alignment tolerance in forming the via. As illustrated in FIG. 3, if via 16 is slightly misaligned, trenching of underlying dielectric layers, such as first dielectric layer 13, may occur during formation of the via. After depositing the second metal layer, metal line 14 fills in the trenched portion of dielectric layer 13, making unwanted contact with substrate 11, or to another conductive region (not illustrated).
As mentioned above, some manufacturers include a conductive landing pad, such as landing pad 18 of device 10 in FIG. 1, to reduce the chances of short circuiting the second metal line 14 to underlying conductive features as a result of via misalignment. Landing pad 18 is formed as part of first metal line 12, and is positioned directly beneath via 16. Since the landing pad is wider than the minimum width of metal line 12, misalignment of via 16 will not be detrimental. As illustrated in FIG. 2, via 16 can be slightly misaligned to either the right or left, yet still lie completely over landing pad 18. With the additional conductive area available, it is less likely that via 16 will fall off the landing pad and trench into underlying dielectric layers.
Although landing pads significantly improve the ability to make reliable contacts between two conductive layers, utilization of landing pads also has a disadvantage. Because a landing pad essentially increases the width of a portion of a metal line, landing pads limit contacted metal line density in a device. Device design rules typically require metal lines to be separated by at least a minimum distance in order to lithographically define and etch the space between adjacent metal lines and to prohibit excessive capacitive coupling between adjacent lines. Since a landing pad is more or less an extended region of a metal line, the minimum distance to an adjacent metal line must be measured from the edge of the landing pad, not from the narrower region of the line. Metal lines with landing pads cannot be formed on as tight a pitch as metal lines without landing pads. For a given number of contacted metal lines, a device which includes landing pads will therefore be larger in area than a device which does not utilize landing pads. Therefore, it would be beneficial if contact between overlying conductive lines could be accomplished reliably without using landing pads and without otherwise increasing device size.